1. Field of the Invention
The present invention relates to a multiplexing apparatus having a BSI-code processing function and a bit interleave function.
In a digital transmission system using optical fibers, etc., a reliable transmission of all kinds of information signals must be guaranteed. To ensure this transmission reliability, a Clear Channel Capability is required in which timing clock signals can be stably extracted from the input information signals without generating code errors, even when the input information signals include consecutive "0"s or "1"s, i.e., direct current components. To realize the Clear Channel Capability, the codes on transmission lines must be bit-sequence independent (BSI).
On the other hand, in a time division multiplex system, a digital hierarchy including many groups from the lowest-order group to the highest-order group has been developed. In addition, attempts have been made to develop a synchronous multiplex system which can realize a multiplex transmission without inserting, at each multiplexing process in each multiplexing circuit in each group, control signals such as frame synchronous signals, so that the increase of the transmission speed due to the insertion of the control signals is not caused after each multiplexing process. By this system, the transmission speed in each multiplexing circuit is, therefore, an integer multiple of a basic PCM signal speed, and thus in each multiplexing circuit, signal processing can be carried out only under the control of the basic clock signal.
To realize the above described synchronous multiplex system, PCM signals having a basic signal transmission speed are given with frame structures provided with multiplexing control signals such as frame synchronous signals and channel numbers of channels to be multiplexed. By this frame structure, the signal speed after the multiplexing is made an integer multiple of the basic PCM signal speed. Thus, a synchronous multiplexing system, which is different from conventional stuffing, is realized. The synchronous multiplexing technique, however, has been devised while taking only the multiplexing system into account, and, therefore, is not satisfactory as a transmission system with the clear channel capability. Namely, no consideration has been given in the synchronous multiplexing system to realizing the BSI of transmission line codes. Therefore, there is a need for a constitution which takes into account the BSI of the transmission system as well as the synchronous multiplexing system.
2. Description of the Related Art
Conventionally, the BSI process of digital transmission codes is realized in a transmission terminal equipment, and a time division multiplexing process, etc., is usually carried out in a multiplexing unit. For this, a signal speed of the PCM hierarchy is used as an interfacing speed between the time division multiplexing process and the transmission terminal equipment. Accordingly, the transmission terminal equipment which receives multiplexed PCM signals must carry out a speed conversion of the PCM signals by executing the BSI process such as an 8B1C (8th-bit one-complement by which one block becomes 9 bits) or a 5B6B (5th-bit 6-bit by which one block becomes 6 bits) and transmit the speed-converted signals to a transmission line. Further, at a receiving station, the signals are subjected to a reverse BSI process, a speed conversion process and a demodulating process, and transmitted to a multiplex converter. In this way, the BSI process is executed within the transmission terminal equipment, as later described in more detail with reference to the drawings.
As described above, in a conventional digital multiplex transmission system, the multiplexing system and the transmission system (BSI, etc.,) are provided separately. Therefore, even if a frame constitution which is adequate for the multiplexing system is adopted, that is, even if information signals with a basic PCM signal speed are provided in advance with a frame constitution to which control signals such as frame synchronous signals and channel numbers of channels to be multiplexed are added for the synchronous multiplexing and demultiplexing processes, the transmission terminal equipment treats these control signals and frame synchronous signals only as information signals. The conventional BSI process, such as a BSI bit insertion and removal, necessary for the transmission system, is carried out in each transmission terminal equipment. Therefore, in each transmission equipment, the multiplexed signal having a regularized speed of, for example, an integer multiple of the basic PCM signal speed, must be converted into a signal with the BSI having an increased speed. Because of the speed conversion, the advantage of the multiplexing system of the digital hierarchy utilizing the basic PCM signal speed is lost in the transmission equipment. Further, due to the necessity of the speed conversion, the hardware scale of the transmission equipment becomes large and expensive.